vishay siliconix sie812df document number: 74337 s09-1337-rev. b, 13-jul-09 www.vishay.com 1 n-channel 40-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? gen ii power mosfet ? ultra low thermal resistance using top- exposed polarpak ? package for double-sided cooling ? leadframe-based new encapsulated package - die not exposed - same layout regardless of die size ? low q gd /q gs ratio helps prevent shoot-through ? 100 % r g and uis tested ? compliant to rohs directive 2002/95/ec applications ?vrm ? dc/dc conversion: low-side ? synchronous rectification product summary v ds (v) r ds(on) ( ) e i d (a) a q g (typ.) silicon limit package limit 40 0.0026 at v gs = 10 v 163 60 52 nc 0.0034 at v gs = 4.5 v 143 60 package drawing www.vishay.com/doc?72945 to p v ie w bottom v ie w top s u rface is connected to pins 1, 5, 6, and 10 p o l ar pak 10 d s s g d d s s g d 1 432 5 67 89 d dsg d 5 4 3 2 1 6 7 8 9 10 orderin g information: sie812df -t1-e3 (lead (p b )-free) sie812df -t1-ge3 (lead (p b )-free and halogen-free) for related documents www.vishay.com/ppg?74337 n -channel mosfet g d s notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. see solder profile ( www.vishay.com/doc?73257 ). the polarpak is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufactu ring. a solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. rework conditions: manual soldering with a sold ering iron is not recommended for leadless components. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 40 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 163 (silicon limit) a 60 a (package limit) t c = 70 c 60 a t a = 25 c 33 b, c t a = 70 c 27 b, c pulsed drain current i dm 100 continuous source-drain diode current t c = 25 c i s 60 a t a = 25 c 4.3 b, c single pulse avalanche current l = 0.1 mh i as 50 avalanche energy e as 125 mj maximum power dissipation t c = 25 c p d 125 w t c = 70 c 8 0 t a = 25 c 5.2 b, c t a = 70 c 3.3 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) d, e 260
www.vishay.com 2 document number: 74337 s09-1337-rev. b, 13-jul-09 vishay siliconix sie812df notes: a. surface mounted on 1" x 1" fr4 board. b. maximum under steady state conditions is 6 8 c/w. c. measured at source pin ( on the side of the package). notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, b t 10 s r thja 20 24 c/w maximum junction-to-case (drain top) steady state r thjc (drain) 0. 8 1 maximum junction-to-case (source) a, c r thjc (source) 2.2 2.7 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 40 v v ds temperature coefficient v ds /t j i d = 250 a 45.5 mv/c v gs(th) temperature coefficient v gs(th) /t j - 7.1 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.5 2.3 3 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 40 v, v gs = 0 v 1 a v ds = 40 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 25 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 25 a 0.0022 0.0026 v gs = 4 .5 v, i d = 25 a 0.002 8 0.0034 forward transconductance a g fs v ds = 20 v, i d = 25 a 154 s dynamic b input capacitance c iss v ds = 20 v, v gs = 0 v, f = 1 mhz 8 300 pf output capacitance c oss 8 00 reverse transfer capacitance c rss 360 total gate charge q g v ds = 20 v, v gs = 10 v, i d = 25 a 111 170 nc v ds = 10 v, v gs = 4.5 v, i d = 20 a 52 8 0 gate-source charge q gs 25 gate-drain charge q gd 15 gate resistance r g f = 1 mhz 1.15 1.7 tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 2 i d ? 10 a, v gen = 4.5 v, r g = 1 50 75 ns rise time t r 265 400 turn-off delay time t d(off) 50 75 fall time t f 10 15 tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 2 i d ? 10 a, v gen = 10 v, r g = 1 20 30 rise time t r 15 25 turn-off delay time t d(off) 60 90 fall time t f 10 15 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 60 a pulse diode forward current a i sm 100 body diode voltage v sd i s = 10 a 0. 8 1.2 v body diode reverse recovery time t rr i f = 10 a, di/dt = 100 a/s, t j = 25 c 50 75 ns body diode reverse recovery charge q rr 65 100 nc reverse recovery fall time t a 27 ns reverse recovery rise time t b 23
document number: 74337 s09-1337-rev. b, 13-jul-09 www.vishay.com 3 vishay siliconix sie812df typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 20 40 60 80 100 0.0 0.1 0.2 0.3 0.4 0.5 v gs = 10 v thr u 6 v 3 v v ds - drain-to-so u rce v oltage ( v ) ) a ( t n e r r u c n i a r d - i d 4 v 5 v 0.0020 0.0022 0.0024 0.0026 0.0028 0 . 0030 0 20406080100 v gs = 10 v i d - drain c u rrent (a) v gs = 4.5 v r ds(on) - ( ) e c n a t s i s e r - n o 0 2 4 6 8 10 0 20406080100120 i d = 25 a ) v ( e g a t l o v e c r u o s - o t - e t a g - q g - total gate charge (nc) v gs v ds = 32 v v ds = 20 v transfer characteristics capacitance on-resistance vs. junction temperature 0 4 8 12 16 20 01234 t c = 125 c 25 c - 55 c v gs - gate-to-so u rce v oltage ( v ) ) a ( t n e r r u c n i a r d - i d c rss 0 2000 4000 6000 8000 10 000 0 5 10 15 20 25 30 35 40 c oss c iss v ds - drain-to-so u rce v oltage ( v ) ) f p ( e c n a t i c a p a c - c 0.6 0.8 1.0 1.2 1.4 1.6 1 . 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v , 4.5 v i d = 25 a t j - j u nction temperat u re (c) r ) n o ( s d e c n a t s i s e r - n o - ) d e z i l a m r o n (
www.vishay.com 4 document number: 74337 s09-1337-rev. b, 13-jul-09 vishay siliconix sie812df typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage v sd - so u rce-to-drain v oltage ( v ) ) a ( t n e r r u c e c r u o s - i s 1.0 1 10 100 0.0 0.2 0.4 0.6 0.8 t j = 25 c t j = 150 c 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a t j - temperat u re (c) v ) h t ( s g ) v ( on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.0020 0.0025 0.0030 0.0035 0.0040 0.0045 0 . 00 5 0 2 4 6 8 10 i d = 25 a v gs - gate-to-so u rce v oltage ( v ) r ds(on) - ( ) e c n a t s i s e r - n o e c r u o s - o t - n i a r d t a = 25 c t a = 125 c 0 30 5 0 10 20 ) w ( r e w o p time (s) 40 10 1000 1 0.1 0.01 100 safe operating area, junction-to-ambient 0.01 0.1 1 10 100 100 1 0.01 10 0.1 t a = 25 c single p u lse 1 ms 10 ms 100 ms dc 1 s 10 s b v dss limited limited b y r ds(on) * v ds - drain-to-so u rce v oltage ( v ) * v ds > minim u m v gs at w hich r ds(on) is specified i d - drain c u rrent (a)
document number: 74337 s09-1337-rev. b, 13-jul-09 www.vishay.com 5 vishay siliconix sie812df typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 20 40 60 80 100 120 140 160 180 0 25 50 75 100 125 150 i d ) a ( t n e r r u c n i a r d - t c - case temperat u re (c) package limited power derating, junction-to-case 0 20 40 60 80 100 120 140 25 50 75 100 125 150 t c - case temperat u re (c) ) w ( n o i t a p i s s i d r e w o p
www.vishay.com 6 document number: 74337 s09-1337-rev. b, 13-jul-09 vishay siliconix sie812df typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?74337 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 110 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 55 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-case (drain top) 10 -3 10 -2 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t 0.02 single p u lse normalized thermal transient impedance, junction-to-source 10 -3 10 -2 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t 0.02 single p u lse
document number: 72945 www.vishay.com revision: 11-aug-08 1 package information vishay siliconix polarpak? option l v ie w a v ie w a (bottom v ie w ) prod u ct datasheet/information page contain links to applica b le package dra w ing. detail z 5 d 4 ss 32 g 1 d d 1 10 d d s gs 4 23 (top v ie w ) z 5 6 d 9 g s 8 7 s 10 d gs s 7 9 8 6 d a a m4 m4 m3 m3 m2 m1 t5 t4 t1 t2 t3 t3 t5 d1 d a1 c a e1 e 0.26 0.20 0.33 0.5 8 0.13 0.25 0.39 b 5 b 5 b 5 k4 k4 k1 k2 k3 k3 p1 p1 b 4 b 4 b 1 h1 h4 b 3 h3 h1 h2 b 1 b 2 p1 p1
www.vishay.com document number: 72945 2 revision: 11-aug-08 package information vishay siliconix notes millimeters govern over inches. millimeters inches dim min. nom. max. min. nom. max. a 0.75 0.80 0.85 0.030 0.031 0.033 a1 0.00 - 0.05 0.000 - 0.002 b1 0.48 0.58 0.68 0.019 0.023 0.027 b2 0.41 0.51 0.61 0.016 0.020 0.024 b3 2.19 2.29 2.39 0.086 0.090 0.094 b4 0.89 1.04 1.19 0.035 0.041 0.047 b5 0.23 0.33 0.43 0.009 0.013 0.017 c 0.20 0.25 0.30 0.008 0.010 0.012 d 6.00 6.15 6.30 0.236 0.242 0.248 d1 5.74 5.89 6.04 0.226 0.232 0.238 e 5.01 5.16 5.31 0.197 0.203 0.209 e1 4.75 4.90 5.05 0.187 0.193 0.199 h1 0.23 - - 0.009 - - h2 0.45 - 0.56 0.018 - 0.022 h3 0.31 0.41 0.51 0.012 0.016 0.020 h4 0.45 - 0.56 0.018 - 0.022 k1 4.22 4.37 4.52 0.166 0.172 0.178 k2 1.08 1.13 1.18 0.043 0.044 0.046 k3 1.37 - - 0.054 - - k4 0.24 - - 0.009 - - m1 4.30 4.50 4.70 0.169 0.177 0.185 m2 3.43 3.58 3.73 0.135 0.141 0.147 m3 0.22 - - 0.009 - - m4 0.05 - - 0.002 - - p1 0.15 0.20 0.25 0.006 0.008 0.010 t1 3.48 3.64 4.10 0.137 0.143 0.161 t2 0.56 0.76 0.95 0.022 0.030 0.037 t3 1.20 - - 0.047 - - t4 3.90 - - 0.153 - - t5 0 0.18 0.36 0.000 0.007 0.014 0 10 12 0 10 12 ecn: t-08441-rev. c, 11-aug-08 dwg: 5946
application note 826 vishay siliconix www.vishay.com document number: 73491 6 revision: 21-jan-08 application note recommended minimum pads for polarpak ? option l and s 0.955 (0.03 8 ) 0.410 (0.016) 0.510 (0.020) 0.510 (0.020) 7.300 (0.2 8 7) 0.955 (0.03 8 ) 0. 8 95 (0.035) 0. 8 95 (0.035) 0.5 8 0 (0.023) 2.290 (0.090) 0.510 (0.020) 0.5 8 0 (0.023) 4.520 (0.17 8 ) 6.310 (0.24 8 ) + recommended minim u m for polarpak option l and s dimensions in mm/(inches) n o external traces w ithin broken lines dot indicates gate pin (part marking) return to index
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